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QN8035 single-chip low-power fm receiver for portable devi ces preliminary rev0.08(02/10) copyright?2010byquinticcorpora tion page1 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductu nderdevelopment.characteristicsandspecification saresubjecttochangewithoutnotice.. ________ general description ________ _________typical applications________ theQN8035isahighperformance,lowpower;full featuredsinglechipstereofmreceiverdesignedfo rcell phones,mp3players.theQN8035alsosupports rds/rbdsdatareception. ? cellphones/pdas/smartphones ? portableaudio&mediaplayers ? mp3/mp4player,pmp,pnd _______________________________ key features ____ _______________________ worldwide fm band coverage ? 60mhzto108mhzfullbandtuningin 50/100/200khzstepsizes ? 50/75 m sdeemphasis ease of integration ? smallfootprint,availablein2.5x2.5qfn16and 3x3msop10packages ? 32.768khzandmultiplemhzclocksinput ? i 2 ccontrolinterface very low power consumption ? 13matypical ? v cc :2.7~5.0v,indegratedldo,supportbattery directconnection ? powersavingstandbymode ? lowshutdownleakagecurrent ? accommodate1.6~3.6vdigitalinterface adaptive noise cancellation volume control high performance ? superiorsensitivity,betterthan1.5v emf ? 63dbstereosnr,0.03%thd ? integratedadaptivenoisecancellation(snc,hcc, sm) ? improvedautochannelseek ? l/rseparation45db rds/rbds 1. supportsusandeuropeandataservices ? superiorsensitivity,betterthan8.9v emf robust operation ? 25 0 cto+85 0 coperation ? esdprotectiononallinputandoutputpads QN8035 functional blocks: de dede de emph emph emph emph vcc vcc vcc vcc 2 22 2. .. .7 77 7C CC C5 55 5. .. .0 00 0v vv v aro aro aro aro alo alo alo alo de dede de mpx mpx mpx mpx dspfsm dspfsm dspfsm dspfsm rds rds rds rds phy phy phy phy rfi rfi rfi rfi rxant rxant rxant rxant 10 1010 10 f ff f tune tune tune tune de dede de mod mod mod mod controlinterface controlinterface controlinterface controlinterface xclk xclk xclk xclk sda sda sda sda scl scl scl scl int intint int voltage voltage voltage voltage regulator regulator regulator regulator i ii i 2 22 2 ccontroller ccontroller ccontroller ccontroller ordering information appears at section 7. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page2 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. contents 1 pinassignment ..................................... ................................................... ................................................... ........5 2 electricalspecifications .......................... ................................................... ................................................... .....5 3 functionaldescription ............................. ................................................... ................................................... ..10 3.1 fmreceiver ........................................ ................................................... ..................................10 3.2 audioprocessing ................................... ................................................... ................................11 3.3 rds/rbds ........................................... ................................................... .................................12 3.4 autoseek(cca).................................... ................................................... ...............................12 4 controlinterfaceprotocol ......................... ................................................... ................................................... .13 5 applications ....................................... ................................................... ................................................... .........14 5.1 typicalapplicationschematic...................... ................................................... ........................14 5.2 powersupply....................................... ................................................... ..................................14 5.3 clockselectionandsetting ........................ ................................................... ...........................14 5.4 audiointerface .................................... ................................................... ..................................15 5.5 antenna............................................ ................................................... ......................................15 5.6 reset .............................................. ................................................... ........................................15 5.7 receivemode ....................................... ................................................... .................................15 5.8 idleandstandbymodes............................. ................................................... .........................15 5.9 volumecontrol ..................................... ................................................... ................................15 5.10 channelsetting.................................... ................................................... ..................................15 5.11 hardwareinterrupt................................. ................................................... ................................16 5.12 rds/rbds ........................................... ................................................... .................................16 5.13 programmingguide.................................. ................................................... .............................16 6 usercontrolregisters............................. ................................................... ................................................... ...18 7 orderinginformation ............................... ................................................... .......................................33 8 packagedescription ................................ ................................................... ................................................... ...34 9 solderreflowprofile .............................. ................................................... ................................................... ...38 9.1 packagepeakreflowtemperature .................... ................................................... ...................38 9.2 classificationreflowprofiles ..................... ................................................... ..........................38 9.3 maximumreflowtimes ............................... ................................................... ........................39 free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page3 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. revision history revision change description date 0.1 draft 12/11/09 0.02 modifythereg05h 01/14/10 0.03 1. modifythefigure7i 2 cserialcontrolinterfaceprotocol 2. updatethechapter5; 3. updatethetable10summaryofusercontrolregiste rs 01/18/10 0.04 modifythedatainchapter2. 01/18/10 0.05 modifythetestconditionsinchapter2 01/20/10 0.06 modifythereg05h 01/25/10 0.07 modifythechapter5. 02/10/10 0.08 1. modifythedescriotioninkeyfeatureshighperfor mance; 2. modifythefigureQN8035functionalblocks; 3. add3symbolsintable6:r load, c load thd driver ; 4. replacethefigure8andfigure9; 5. modifynotes:seealsopll_div[12:0]intable5 6. modifysomemistakesinsection5.3 7. replacefigure152.5x2.5qfn16carriertape 02/22/10 free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page5 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 1 pin assignment figure 1 QN8035-ncna ncna pin out qfn16 2.5x2.5mm figure 2 QN8035-sana pin out msop10 3x3mm table 1: pin descriptions msop10 qfn24 name description 1 1 vcc voltagesupply 2 2 alo analogaudiooutputCleftchannel 3 3 aro analogaudiooutputCrightchannel 4 4 agnd ground 5 5 rfi fmreceiverrfinput 6 gnd rfground 7 12 xclk ifusinganexternalclocksource,inject fromthispin 8 13 gnd ground 6 14 int interruptoutput,activelow,needpullup externally 9 15 scl clockfori 2 cserialbus. 10 16 sda bidirectionaldatalinefori 2 cserialbus. 7/8/9/10/11 nc noconnect. (top view) aro aro aro aro s ss s c cc c l ll l 13 1313 13 1 11 1 nc ncnc nc 11 1111 11 xclk xclk xclk xclk 12 1212 12 nc ncnc nc 10 1010 10 9 99 9 5 55 5 3 33 3 alo alo alo alo 2 22 2 agnd agnd agnd agnd 4 44 4 s ss s d dd d a aa a 1 11 1 6 66 6 i ii i n nn n t tt t 1 11 1 4 44 4 n nn n c cc c g gg g n nn n d dd d 6 66 6 exposedpad exposedpad exposedpad exposedpad pin pin pin pin17 1717 17 farside farside farside farside nc ncnc nc g gg g n nn n d dd d vcc vcc vcc vcc r rr r f ff f i ii i 1 11 1 5 55 5 n nn n c cc c 7 77 78 88 8 1 11 1 2 22 2 3 33 3 4 44 4 5 55 5 10 1010 10 9 99 9 8 88 8 7 77 7 6 66 6 sda sda sda sda scl scl scl scl gnd gnd gnd gnd xclk xclk xclk xclk int intint int vcc vcc vcc vcc alo alo alo alo aro aro aro aro agnd agnd agnd agnd rfi rfi rfi rfi free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page5 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 2 electrical specifications table 2: absolute maximum ratings symbol parameter conditions min max unit v bat supplyvoltage vcctognd 0.3 5 v v io logicsignallevel cen,scl,sda,int tognd 0.3 3.6 v t s storagetemperature 55 +150 o c table 3: recommended operating conditions symbol parameter conditions min typ max unit vcc supplyvoltage vcctognd 2.7 3.3 5.0 v t a operatingtemperature 25 +85 o c rf in rfinputlevel 1 peakinputvoltage 0.3 v v io digitali/ovoltage 1.6 3.6 v notes: 1.atrfinputpin,rfi. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page6 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. table 4: dc characteristics (typicalvaluesareatvcc=3.3vandt a =25 o c). symbol parameter conditions min typ max unit i rx receivemodesupplycurrent 13 ma i idle idlemodesupplycurrent idlemode tbd ma i stby standbymodesupplycurrent standbymode tbd m a i pdn powerdownleakagecurrent powerdown tbd m a interface v oh highleveloutputvoltage 0.9*v io v v ol lowleveloutputvoltage 0.1*v io v v ih highlevelinputvoltage 0.7*v io v v il lowlevelinputvoltage min (0.3*vio ,0.6) v table 5: ac characteristics (typicalvaluesareatvcc=3.3vandt a =25 o c). symbol parameters conditions min typ max unit f xtal crystalorclock frequency 0.03276840 1 mhz f xtal_err crystalfrequency accuracy overtemperature,andaging 20 20 ppm notes: 1. seealsopll_div[12:0] free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page7 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. table 6: receiver characteristics (typicalvaluesareatvcc=3.3v,fcarrier=88mhz andt a =25 o c). symbol parameters conditions min typ max unit s rx fmsensitivity (s+n)/n=26db tbd m v emf s rds rdssensitivity ber5%,averageover2000 blocks tbd m v emf ip3 inputreferredip3 atmaximumgain tbd db m v rej am amsuppression 70 db r in rfinputimpedance atpinrfi 1 k w s rx_adj adjacentchannel rejection 200khzoffset 50 db s rx_alt alternatechannel rejection 400khzoffset 50 db mono, d f=22.5khz 1 57 snr audio_in audiosnr stereo, d f=67.5khz, d f pilot = 6.75khz 63 db mono, d f=75khz 0.03 % thd audio_in audiothd stereo, d f=67.5khz, d f pilot = 6.75khz 0.03 % a lr_in l/rseparation 40 db att pilot pilotrejection 66 db b lr l/rchannelimbalance landrchannelgainimbalance at1khzoffsetfromdc 1 db petc=1 71.3 75 78.7 m s t emph 1 deemphasistime constant petc=0 47.5 50 52.5 m s v audio_out audiooutputvoltage peakpeak,singleended 1 1. 4 v r load audiooutputloading resistance 0.6 k w c load audiooutputloading capacitance 20 pf rssi err rssiuncertainty 3 3 db r load audiooutputloading resistance 32 w c load audiooutputloading capacitance 20 pf r load =16 w , 500mv p output 53 db thd driver audiothdafter earphonedriver r load =32 w , 500mv p output 61 db notes: 1. guaranteedbydesign. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page8 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. table 7: timing characteristics (typicalvaluesareatvcc=3.3vandt a =25 o c). symbol parameter conditions min typ max unit t pup chippoweruptime 1 fromrisingedgeofcento validaudiooutput. 0.6 sec tmout[1:0]=00 1 tmout[1:0]=01 3 tmout[1:0]=10 5 t astby autostandbytime 2 tmout[1:0]=11 never min t chsw channelswitching time 1 fromanychanneltoany channel. 0.12 sec receiver timing t wkup wakeuptimefrom standbytoreceive standbytorxmode. 200 ms t tune tunetime perchannelduringcca. 5 ms notes: 1. guaranteedbydesign. 2. chipautomaticallygoesfromidletostandbymode; tmout=11equivalenttoautostandbydisabled. table 8: i 2 c interface timing characteristics (typicalvaluesareatvcc=3.3vandt a =25 o c). symbol parameter conditions min typ max unit f scl i 2 cclockfrequency 400 khz t low clocklowtime 1.3 m s t hi clockhightime 0.6 m s t st sclinputtosda fallingedgestart 1,3 0.8 m s t sthd sdafallingedgeto sclfallingedgestart 3 0.8 m s t rc sclrisingedge 3 levelfrom30%to70% 300 ns t fc sclfallingedge 3 levelfrom70%to30% 300 ns t dthd sclfallingedgeto nextsdarisingedge 3 20 ns t dtc sdarisingedgeto nextsclrisingedge 3 900 ns t stp sclrisingedgeto sdarisingedge 2,3 0.6 m s t w durationbeforerestart 3 1.3 m s c b scl,sdacapacitive 10 pf free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page9 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. symbol parameter conditions min typ max unit loading 3 notes: 1. startsignalingofi 2 cinterface. 2. stopsignalingofi 2 cinterface. 3. guaranteedbydesign. figure 3 i 2 c serial control interface timing diagram free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page10 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 3 functional description theQN8035isahighperformance,lowpower,single chipfmreceivericthatsupportsworldwidefmbro adcastband(60 to108mhz).rds/rbdsdataserviceisalsosupporte d. de dede de emph emph emph emph vcc vcc vcc vcc 2 22 2. .. .7 77 7C CC C5 55 5. .. .0 00 0v vv v aro aro aro aro alo alo alo alo de dede de mpx mpx mpx mpx dspfsm dspfsm dspfsm dspfsm rds rds rds rds phy phy phy phy rfi rfi rfi rfi rxant rxant rxant rxant 10 1010 10 f ff f tune tune tune tune de dede de mod mod mod mod controlinterface controlinterface controlinterface controlinterface xclk xclk xclk xclk sda sda sda sda scl scl scl scl int intint int voltage voltage voltage voltage regulator regulator regulator regulator i ii i 2 22 2 ccontroller ccontroller ccontroller ccontroller figure 4 q n8035 functional blocks theQN8035integratesfmreceivefunctions,includi ng rffrontendcircuits(lna,mixerandchannelselec tive filteretc),afullydigitizedfmdemodulator,mpx decoder,deemphasisandaudioprocessing(sm,hcc, andsnc).advanceddigitalarchitectureenables superiorreceiversensitivityandcrystalclearaud io.the QN8035'sautoseekfunctionenablesautomaticchann el selectionforbettersoundquality. theQN8035supportsasmallfootprint,highlevelo f integrationandmultipleclockfrequencies.these featuresmakeiteasytobeintegratedintoavarie tyof smallformfactor,lowpowerportableapplications. low phasenoisedigitalsynthesizersandextensiveonc hip autocalibrationensuresrobustandconsistent performanceovertemperatureandprocessvariations .an integratedvoltageregulatorenablesdirectconnect iontoa liionbatteryandprovideshighpsrrforsuperior noise suppression.alowpoweridleandstandbymode extendsbatterylife. 3.1 fm receiver the QN8035 receiver uses a highly digitized lowif architecture, allowing for the elimination of exter nal componentsandfactoryadjustments. thereceivedrfsignalisfirstamplifiedbyanint egrated lnaandthendownconvertedtoanintermediate frequency(if)viaaquadraturemixer.toimprovei mage rejection(imr),thequadraturemixercanbeprogra mmed tobeathighsideorlowsideinjection.whenthe rf frequencyisgreaterthanthelocaloscillator(lo) ,imageis atlowside;otherwise,imageisathighside(refe rto reg02hformoreinformation).anintegratedifchan nel filterrejectsoutofchannelinterferencesignals. agcis alsoperformedsimultaneouslytooptimizethesigna lto noiseratioaswellaslinearityandinterferencer ejection. thefilteredsignalisdigitizedandfurtherproces sedwitha digitalfmdemodulatorandmpxdecoder.audio processingisthenperformedbasedonreceivedsign al qualityandchannelcondition.twohighqualityau dio dacsareintegratedonchiptodrivetheaudiooutp ut.the rdssignalwillalsobedecodedifrdsreceptionis enabled. areceivesignalstrengthindicator(rssi)isprovi dedand canbereadfromrssidb[7:0].figure5showsthec urve ofrssivs.differentrfinputlevels.autoseekut ilizes rssitosearchforavailablechannels. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page11 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. thefollowingfigureismeasuredatfm=88mhz.ther ssicurveisnotvariedbyfmfrequency. figure 5 rssi vs rf input 3.2 audio processing thempxsignalafterfmdemodulationiscomprisedo f leftandrightchannelsignal,pilotandrdssignal inthe followingway: [ ] [ ] 0 0 0 ( ) ( ) ( ) ( ) ( ) sin(4 2 ) sin(2 ) ( ) sin(6 3 ) m t l t r t l t r t ft ft d t ft p q a p q p q = + + - + + + + + here,l(t)andr(t)correspondtotheaudiosignals onthe left andrightchannelsrespectively,f = 19 khz, q isthe initial phase of pilottone and a isthe magnitudeof the pilot tone, and d(t) is the rds signal. in stereo mode, bothlandrarerecoveredbydempx.inmonomode, onlythel+rportionofaudiosignalexists.l(t)a ndr(t) arerecoveredbydempx. inreceivemode,stereonoisecancellation(snc)fo rfm only, high cut control (hcc) and soft mute (sm) are supported. stereo noise suppression is achieved by gradually combining the left and right signals to b e a mono signal as the received signal quality degrades . snc,hccandsmarecontrolledbysnrandmultipath channel estimation results. the three functions wi ll be archivedautomaticallyinthedevice. the QN8035 has an integrated mono or stereo audio status indicator. there is also a read st_mo_rx (reg04h [0]) bit to get sound information. in addit ion, there also is a force mono function to constrain ou tput monoinreg04h. toimprovethesignaltonoiseratioofthefmrece iver byreducingtheeffectofhighfrequencyinterferen ceand noise,thedeviceintegratesatechniqueknownasd e emphasis.therearetwoselectabletimeconstants( 75us and50us)supported. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page12 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. figure 6 audio response the audio output can be muted with the mute_en (reg14h[7])bitandtheoutputcanalsobereplaced byan internally generated 1khz tone whenever the rfi has a rfsignalinput. 3.3 rds/rbds theQN8035supportsrds/rbdsdatareceptioninfm mode,includingstationid,metadata,tmcinformat ion, etc.theintegratedrdsprocessorperformsallsym bol encoding/decoding,blocksynchronization,errordet ection andcorrectionfunctions.rds/rbdsdatacommunicat es withanexternalmcuthroughtheserialcontrolint erface. 3.4 auto seek (cca) in receive mode, the QN8035 can automatically tune to stationswithgoodsignalquality.theautoseekf unction isreferredtocca(clearchannelassessment). free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page13 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 4 control interface protocol theQN8035supportsthestandardi 2 cserialinterfaces.at poweron,allregisterbitsaresettodefaultvalu es. i 2 c serial control interface the i 2 c bus is a simple bidirectional bus interface. the busrequiresonlyserialdata(sda)andserialcloc k(scl) signals. the bus is 8bit oriented. each device is recognized with a unique address. each register is also recognized with a unique address. the i 2 c bus operates withamaximumfrequencyof400khz.eachdataput on thesdamustbe8bitslong(byte)frommsbtolsb and each byte sent should be acknowledged by an ack bit. in case a byte is not acknowledged, the trans mitter should generate a stop condition or restart the transmission. if a stop condition is created befor e the wholetransmissioniscompleted,theremainingbyte swill keep their old setting. in case a byte is not compl etely transferred,itwillbediscarded. data transfer to and from the QN8035 can begin when a start condition is created. this is the case if a t ransition fromhightolowonthesdalineoccurswhilethes cl ishigh.thefirstbytetransferredrepresentsthe address oftheicplusthedatadirection.thedefaultica ddressis 0010000. a low lsb of this byte indicates data transmission (write), while a high lsb indicatesda ta request (read). this means that the first byte to be transmitted to the QN8035 should be 20 for a writ e operationor21forareadoperation. the second byte is the starting register address (n ) for write/readoperation.thefollowingbytesareregis terdata for address n, n+1, n+2, etc. there is no limit on the numberofbytesineach transmission.atransmissio n can be terminated by generating a stop condition, which is sdatransitionfromlowtohigh whilesclis high. forwriteoperation,masterstopstransmissionafte rthelast byte. for read operation, master doesnt send ack a fter receivingthelastreadbackbyte;thenstopsthet ransmissio thetimingdiagramsbelowillustratebothwriteand readoperations. i ii i 2 22 2 cwriteoperation cwriteoperation cwriteoperation cwriteoperation i ii i 2 22 2 creadoperation creadoperation creadoperation creadoperation scl scl scl scl sda sda sda sda databyte databyte databyte databyte2 22 2 ackby ackby ackby ackby qn qnqn QN8035 8035 8035 8035 ackby ackby ackby ackby ackby ackby ackby ackby qn qnqn QN8035 8035 8035 8035 databyte databyte databyte databyte3 33 3 databyten databyten databyten databyten stop stop stop stop qn qnqn QN8035 8035 8035 8035 qn qnqn QN8035 8035 8035 8035 qn qnqn QN8035 8035 8035 8035 start start start start i ii i 2 22 2 c c c c slave slave slave slave address address address address r rr r/ // /w ww w ackby ackby ackby ackby baseaddress baseaddress baseaddress baseaddress databyte databyte databyte databyte1 11 1 ackby ackby ackby ackby ackby ackby ackby ackby a aa a7 77 7 a aa a6 66 6 a aa a5 55 5 a aa a4 44 4 a aa a3 33 3 a aa a2 22 2 a aa a1 11 1 a aa a0 00 0 d dd d7 77 7 d dd d6 66 6 d dd d5 55 5 d dd d4 44 4 d dd d3 33 3 d dd d2 22 2 d dd d1 11 1 d dd d0 00 0 scl scl scl scl sda sda sda sda scl scl scl scl sda sda sda sda scl scl scl scl sda sda sda sda a aa a7 77 7 a aa a6 66 6 a aa a5 55 5 a aa a4 44 4 a aa a3 33 3 a aa a2 22 2 a aa a1 11 1 a aa a0 00 0 qn qnqn QN8035 8035 8035 8035 qn qnqn QN8035 8035 8035 8035 start start start start i ii i 2 22 2 c c c c slave slave slave slave address address address address r rr r/ // /w ww w ackby ackby ackby ackby baseaddress baseaddress baseaddress baseaddress ackby ackby ackby ackby d dd d7 77 7 d dd d6 66 6 d dd d5 55 5 d dd d4 44 4 d dd d3 33 3 d dd d2 22 2 d dd d1 11 1 d dd d0 00 0 d dd d7 77 7 d dd d6 66 6 d dd d5 55 5 d dd d4 44 4 d dd d3 33 3 d dd d2 22 2 d dd d1 11 1 d dd d0 00 0 qn qnqn QN8035 8035 8035 8035 micro micro micro micro start start start start i ii i 2 22 2 c c c c slave slave slave slave address address address address r rr r/ // /w ww w ackby ackby ackby ackby ackby ackby ackby ackby stop stop stop stop databyte databyte databyte databyte1 11 1 databyten databyten databyten databyten micro micro micro micro ackby ackby ackby ackby d dd d7 77 7 d dd d6 66 6 d dd d5 55 5 d dd d4 44 4 d dd d3 33 3 d dd d2 22 2 d dd d1 11 1 d dd d0 00 0 d dd d7 77 7 d dd d6 66 6 d dd d5 55 5 d dd d4 44 4 d dd d3 33 3 d dd d2 22 2 d dd d1 11 1 d dd d0 00 0 d dd d7 77 7 d dd d6 66 6 d dd d5 55 5 d dd d4 44 4 d dd d3 33 3 d dd d2 22 2 d dd d1 11 1 d dd d0 00 0 qn qnqn QN8035 8035 8035 8035 figure 7 i 2 c serial control interface protocol notes: 1. thedefaulticaddressis0010000. 2. 20forawriteoperation,21forareadoperat ion. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page14 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 5 applications 5.1 typical application schematic figure 8 typical application schematic 5.2 power supply theQN8035providesanintegratedvoltageregulator that requiresonlyonedecouplingcapacitorofabout0.1 ufon thebatterypowersupply. a10ufcapacitorcanbea dded forbestperformance.thesupportedpowersupplyvo ltage rangeis2.7to5.0v. 5.3 clock selection and setting the QN8035 supports various external frequencies cl ock injectionthroughacouplingcapacitor.thefollowi ngfigure showstypicalexternalinjectioncircuitasreferen ce. 1) external clock application: figure 9 external clock input circuit note: 32.768khz or greater than or equal to 1mhz clock canbesupported 2) xtal setting: xtal_div[10:0] can be computed by the following formula, and then wirte its result to reg15h and reg16h[2:0]. xtal_div[10:0]=round(freq xtal /32.768khz). thedefaultvalueis0x01for32.768khzclock. 3) pll configuration: to select the clock frequency set the pll frequency divideraccordingtothefollowingformula: pll_dlt[12:0=round(28.5mhz/(freq xtal /xtal_div[10:0]/512))442368 for example: if clock frequency is 32.768khz, then so pll_dlt[12:0]=round(28500000/(32768/1/512))442368 =2945 translating this numble into a hex result, and then write corresponding value to reg17h and reg16h[7:2]. the default value of this parameter pll_dlt [12:0] is 0 xb81 for32.768khz. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page15 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 5.4 audio interface the QN8035 has a highly flexible analog audio interface. the maximum singleended audiooutputl evel is1.4vpeaktopeakandisaccoupledtoexternal audio driver. an external audio driver should be used whe n drivingtheheadphoneorspeakerdirectly. 5.5 antenna thefollowingcircuitisatypicalapplicationutil izingthe earphonelineasafmantenna.threeferritebeads areused topreventinterferenceofthefmsignalwiththea udio signal.atypicalferritebeadvalueisabout2.5k@ 100mhz. formoreinformationonfmantennadesign,pleaser eferto relatedapplicationnotes. figure 10 earphone line as fm antenna 5.6 reset theQN8035supportssoftwarereset,setreg00h[7]b it hightoresetthedevice. afterreset,thedevicewillenterstandbymode.be fore startingreceivemode,systeminitializationshould be executed. 5.7 receive mode theQN8035supportssoftwaretoenablereceivingfu nction fromlowpowerconsumptionstate.afterpoweringup ,the devicewillstopatstandbymodeautomaticallyafte rgoing throughhardwareandsoftwareinitialization(refer to section5.13),setrxreq(reg00h[4])bithighand stnby(reg00h[5])bitlowtoenterreceivemode. to configure the fm receiver, programmability throu gh registersareprovidedtoselectfrequency,setcha nnelindex, select deemphasis constants (75us or 50us), enabl e audio muteandvolumecontrol. 5.8 idle and standby modes the QN8035featureslowpoweridleandstandbymode s forfaststatetransitionandpowersaving.after powerup, theQN8035willenterstandbymodeautomatically. figure 11 three modes switching as shown in figure 11, standby mode can not directl y enteridlemode. table 9: mode switching modebit stnby (reg00h[5]) rxreq (reg00h[4]) receive 0 1 idle 0 0 standby 1 x thestandbymodeisthehighestprioritymode.ifs tnby (reg00h[5])islowandrxreq(reg00h[4])bitsish igh, thedevicewillenterthereceivemode. stnby and rxreq bits of the reg00h are used for setting all three modes. refer to reg00h for detail ed information. if there is no receiving requirement in a predeter mined time period, the QN8035 should enter standby mode b y setregistertosavepowerconsumption. 5.9 volume control the QN8035 integrates an analog volume controller a nd a digital volume controller to set audio output gain. the digitalgainstepis1db,andtheanaloggainstep is6db.the totalgainrangeis47dbto0db.refertoreg14h formore descriptions. 5.10 channel setting manual channel setting by programming channel index ch[9:0], the rf channe l canbesettoanyfrequencybetween60mhz~108mh zin free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page16 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 50khzsteps.thechannelindexandrffrequencyha vethe followingrelationship: f rf = (60 + 0.05 x channel index), w here f rf is the rffrequencyinmhz. forexample:tosetthereceiverto106.9mhz,thec hannel index can be calculated withthe upper formula as s hown infollowing: channelindex=(106.960)/0.05 =938 thistranslatesintoahexnumber0x3aa.sowrite0 xaa toreg07h[7:0]andwrite0x03toreg0ah[1:0]totu neto thedesiredchannel. auto seek after setting start frequency, stop frequency, sear ching step and search threshold, the auto seek function c an be enabled by setting chsc (reg00h [1]) to one. (refer to section5.133forprogrammingguide). also, autoseek supports a hardware interrupt funct ion. refertosection5.11formoredescriptions. 5.11 hardware interrupt theQN8035supportsahardwareinterruptfunction. itcan generateaninterruptsignaltoamcuduringautos eekor rds reception, in order to relieve the mcu from continuouspollingontheQN8035sregisters. figure 12 interrupt output ifrds_int_en(reg17h[7]))issettohigh,alowpu lseof roughly 4.55ms will be produced on the int pin when a newgroupofdataisreceivedandstoredintordsr egisters inrdsmode. similarly, in cca mode, after cca_int_en (reg17h[6] ) issetto high,the same low pulse willbe generate d onthe int pin when a good quality channel isfoundinthe cca mode. 5.12 rds/rbds in receive mode, setting rdsen (reg00h[3]) bit hig h willenabletherdsfunction.oncethedevicerecei vesan rdssignal,therdssync(reg13h[4])willbehigh.o n reception of a rds signal, if rds_rxtxtupd (reg13h[7]) bit is toggled, or the int pin will out put a 4.55ms low pulse when hardware interrupt function i s enabled by rds_int_en, rds data buffer (reg0bh to reg12h)willbefilled. the results of error checksum on four rds blocks a re then available in status2[3:0] (reg13h[3:0]). if an y checksumbitisnonzero,thecorrespondingrdsbl ockis notvalid.checktheregistermapfordetaileddefi nitionof status2[3:0]. e_detbit(reg13h[6])isusedfordistinguishingwh ether the received rds group contains e (mmbs) block, and rdsc0c1(reg13h[5])bitisusedforjudgingwhether the receivedgroupisagrouporbgroup. 5.13 programming guide 1) system initialization: to initialize the device, the following steps need to be executed. a. after powering up, execute software reset to the QN8035. b. selectinjectionclocktype(sinewaveordigitalw ave), andsetreg01h[7]. c. select clock frequency (32.768 khz or other frequencies), then set xtal_dlv[10:0] (reg15h to reg16h). d. setpll_dlt[12:0]andwritethecomputedresultto reg16h[7:3] and reg17h. for detailed configuration, refertosection5.3. e. software initialization. refer to QN8035 applicatio n note. 2) manual channel tuning a. according to the formula on section 5.10, derive channelindexofthedesiredchannel. b. writechannelindextoreg07handreg0ah[1:0]. c. set chcs (reg00h[1]) bit low to disable the cca functionandselectmanualoperation. d. setthe cca_ch_dis (reg00h[0]) bit highto select manualtuningchannel. e. set rxreq (reg00[4]) bit high and stnby (reg00h[5]bitlowtoenterreceivemode. 3) auto seek (cca) 4.55ms int free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page17 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. a. set start frequency of cca. using the formula on section5.10,calculatechannelindexofstartfreq uency, thenwriteitshexvaluetoreg08handreg0ah[3:2]. b. in the same way calculate channel index of stop frequency, then write its hex value to reg09h and reg0ah[5:4]. c. select step of cca, 50khz, 100khz or 200khz, writecorrespondingvaluetoreg0ah[7:6]bits. d. writesuitablevaluetorxccad[5:0]tosetcca searchingthresholdinreg01h. e. setcca_int_en(reg17h[6])bithightoenable interruptforcca.(optional) f. setthecca_ch_dis(reg00h[0])bitlowtoselect ccaresultastuningchannel. g. setchsc(reg00h[1])bithightoenablecca. h. set rxreq (reg00h [4]) bit high stnby (reg00h[5]bitlowtoenterreceivemode. i. readthech(reg07h)andch_step (reg0ah[1:0])afterthechsc(reg00h[1])bitis low,orwheninterruptfunctionisenabledandthe intpinoutputsalowpulse. j. readthestatus1(reg04h[3])bit.ifitislow,th e cca result is valid, otherwise, discard the result. note :ifinterruptfunctionisused,itisnotnecessar y tocheckstatus1bit. k. according to the values of ch (reg07h) and ch_step(reg0ah[1:0]),calculatechannelresultof cca. l. repeatstep g to k forscanningallgoodchannelsina frequencyband. note: when the start frequency is greater than the stop frequency,thedevicewillsearchdown,andwhenth estart frequency is less than the stop frequency, the devi ce will searchup. 4) rds a. configureQN8035channelasdescribedinmanual channeltuning. b. settherds_int_en(reg17h[7])bithightoenable therdsinterruptfunction.(optional) c. set the rds_only (reg17h [5]) bit high or low (default is low) to select the rds working mode. (optional) d. set the rdsen (reg00h [3]) bit high to enable the rdsfunction. e. checktherdssync(reg13h[4])bit.ifitishigh, the device has received rds signal, otherwise keep waitingorexittherdsmode. f. look for the rds reception indicators. check the rds_rxtxupd (reg13h [7]) bit to monitor whetheritistoggledinreg13h.iftherdsinterru pt function is enabled, low pulse on the int pin is another indicator of the rds reception. if no rds reception,keepwaiting. g. afterrdsindicatorsinstep f aretriggered,readout reg13h [3:0] four bits values to judge whether they areallzeros.ifso,rdsdatainregistersreg0bh to reg12h(rdsd0~rdsd7)arevalid. h. readoutrdsdatafromregistersreg0bhtoreg12h (rdsd0~rdsd7)forfurtherdecoding. i. repeatsteps e to h forcontinuousreceptionofrds data. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page18 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 6 user control registers thisisapreviewlist.numberandconten tofregisterssubjecttochangewithoutnotice thereare25useraccessiblecontrolregisters.all registersnotlistedbelowareformanufacturingu seonly. table 10: summary of user control registers register name user control functions 00h system1 setsdevicemodes. 01h cca setsccaparameters. 02h snr estimaterfinputcnrvalue 03h rssisig inbandsignalrssidbvvalue. 04h status1 systemstatus. 05h cid1 deviceidnumbers. 06h cid2 deviceidnumbers. 07h ch lower8bitsof10bitchannelindex. 08h ch_start lower8bitsof10bitchannelscanst artchannelindex. 09h ch_stop lower8bitsof10bitchannelscansto pchannelindex. 0ah ch_step channelscanfrequencystep.highest2 bitsofchannelindexes. 0bh rdsd0 rdsdatabyte0. 0ch rdsd1 rdsdatabyte1. 0dh rdsd2 rdsdatabyte2. 0eh rdsd3 rdsdatabyte3. 0fh rdsd4 rdsdatabyte4. 10h rdsd5 rdsdatabyte5. 11h rdsd6 rdsdatabyte6. 12h rdsd7 rdsdatabyte7. 13h status2 rdsstatusindicators. 14h vol_ctl audiocontrols. 15h xtal_div0 frequencyselectofreferenceclocks ource 16h xtal_div1 frequencyselectofreferenceclocks ource 17h xtal_div2 frequencyselectofreferenceclocks ource 18h int_ctrl rdscontrol free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page19 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. register bit r/w status: ro r ead o nly:youcannotprogramthesebits. wo w rite o nly:youcanwriteandreadthesebits;thevaluey oureadbackwillbethesameaswritten. r/w r ead/ w rite:youcanwriteandreadthesebits;thevalue youreadbackcanbedifferentfromthevaluewritt en. typically,thevalueissetbythechipitself.thi scouldbeacalibrationresult,agcfsmresult,et c. word : system1 address : 00h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) swrst recal stnby rxreq rdsen force_mo chsc cca_ch_dis wo wo wo wo wo wo wo wo bit symbol default description resetallregisterstodefaultvalues: 0 keepthecurrentvalues. 7 swrst 0 1 resettothedefaultvalues. resetthestatetoinitialstatesandrecalibratea llblocks: 0 noreset.fsmrunsnormally. 6 recal 0 1 resetthefsm.afterthisbitisdeasserted,fsmw illgothrough allthepowerupandcalibrationsequence. requestimmediatelytoenterstandbymodewhatever thechipisinany states. note:stnbyhasthehighestpriority. 0 nonstandbymode. 5 stnby 0 1 enterstandbymode. receivingrequest(overwritesstnby): 0 nonrxmode.eitheridlemode. 4 rxreq 0 1 enterreceivemode. note:stnbymustbesetto0whenenteringrxm ode. rdsenable: 0 nords. 3 rdsen 0 1 rdsenable. forcereceiverinmonomode: 0 notforced.st/monoautoselected 2 force_mo 0 1 forcedinmonomode 1 chsc 0 channelscanmodeenable:combinedwithrxreq,chip scansfor occupiedchannelforreceiving.aftercompletingch annelscanning,thisbit willbeclearedautomatically. forrxscan,thefirstvalidchannelwillbeselect ed. tostartcca,set free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page20 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. chsc(reg0[1])=1.chscwillberesetautomaticall ywhenccais complete.tousethescannedchannel,setcca_ch_di s=0. (cca_ch_discanbesetto0atthesametimechsc=1 ). 0 normaloperation 1 channelscanmodeoperation. ch(channelindex)selectionmethod:seedescriptio nforchregisterat 07hand0ahformoreinformation. 0 chisdeterminedbyinternalcca(channelscan). 0 cca_ch_dis 1 1 chisdeterminedbythecontentinch[9:0]. word : cca address : 01h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) xtal_inj imr rxccad[5] rxccad[4] rxccad[3] rxccad[2 ] rxccad[1] rxccad[0] wo rw wo wo wo wo wo wo bit symbol default description selectthereferenceclocksource 0 injectsinewaveclock 7 xtal_inj 01 1 injectdigitalclock imagerejection.inccadisabledmode(cca_dis=1), thisisusersetvalue.in ccamode,thisisccaselectionreadout 0 lorf,imageisinupperside 5:0 rxccad[5:0] 000000 rxccad [5:0] is used to set the threshold for rx cc a. channel withrssi (dbuv)>(rxccad10)dbuvisselectedasvalidchan nel. word: snr address : 02h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) snrdb[7] snrdb[6] snrdb[5] snrdb[4] snrdb[3] snrdb[ 2] snrdb[1] snrdb[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 snrdb rrrrrrrr inbandsignaltonoiseratio. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page21 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : rssisig address : 03h (ro) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rssidb[7] rssidb[6] rssidb[5] rssidb[4] rssidb[3] r ssidb[2] rssidb[1] rssidb[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rssidb[7:0] rrrrrrrr inbandsignalrssi(receivedsignalstre ngthindicator)dbvvalue: dbv=rssi(withagccorrection)43 free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page22 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : status1 address : 04h (ro) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) cap_sh fsm[2] fsm[1] fsm[0] rxcca_fail rxagcset rxagcerr st_mo_rx ro ro ro ro ro ro ro ro bit symbol default description 7 cap_sh r reserved topfsmstateindicator: fsm[3:0] fsmstatus 000 stby 001 reset 010 cali 011 idle 100 calipll 101 receiveing 110 reserved 6:4 fsm[2:0] rrr 111 rxcca rxccastatusflag:indicateswhetheravalidchanne lisfoundduringrx cca.ifavalidchannelisfound,channelindexwil lstaythere,and rxcca_fail=0;otherwise,itwillstayattheendof scanrangeand rxcca_fail=1. 0 rxccasuccessfulfindsavalidchannel. 3 rxcca_fail r 1 rxccafailstofindavalidchannel. rxagcsettlingstatus: 0 notsettled 2 rxagcset r 1 settled rxagcstatus: 0 noerror 1 rxagcerr r 1 agcerror stereoreceivingstatus: 1 mono 0 st_mo_rx r 0 stereo free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page23 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : cid1 address : 05h (ro) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) cid0[2] cid0[1] cid0[0] cid1[2] cid1[1] cid1[0] cid 2[1] cid2[0] ro ro ro ro ro ro ro ro bit symbol value description 7:5 cid0[2:0] rrr reserved chipidforproductfamily: 000 fm 4:2 cid1[2:0] rrr 000 001~111 reserved chipidforminorrevision: 00 1 01 2 10 3 1:0 cid2[1:0] rr 01 11 4 free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page24 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : cid2 address : 06h (ro) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) cid3[5] cid3[4] cid3[3] cid3[2] cid3[1] cid3[0] cid 4[1] cid4[0] ro ro ro ro ro ro ro ro bit symbol devault description chipidforproductid: 00000111 reserved 100001 QN8035 7:2 cid3[5:0] rrrrrr 100001 100001111111 reserved chipidformajorrevisionis1+cid4 00 1 01 2 10 3 1:0 cid4[3:0] rrrr 00 11 4 word : ch address : 07h (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) ch[7] ch[6] ch[5] ch[4] ch[3] ch[2] ch[1] ch[0] rw rw rw rw rw rw rw rw bit symbol default description 7:0 ch[7:0] 00110000 lower8bitsof10bitchannelindex.channelused forrxhastwo origins,oneisfromchregister(reg07h+reg0ah[ 1:0]),whichcan bewrittenbytheuser,anotherisfromcca/ccs.cc a/ccsselected channelisstoredinaninternalregister,whichis physicallyadifferent registerwithchregister,butitcanbereadoutt hroughregisterchand beusedforrxwhencca_ch_dis(reg0[0])=0. fmchannel:(60+ch*0.05)mhz free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page25 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : ch_start address : 08h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) ch_sta[7] ch_sta[6] ch_sta[5] ch_sta[4] ch_sta[3] c h_sta[2] ch_sta[1] ch_sta[0] wo wo wo wo wo wo wo wo bit symbol default description 7:0 ch_sta[7:0] 00011100 lower8bitsof10bitcca(channelscan) startchannelindex. word : ch_stop address : 09h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) ch_stp[7] ch_stp[6] ch_stp[5] ch_stp[4] ch_stp[3] c h_stp[2] ch_stp[1] ch_stp[0] wo wo wo wo wo wo wo wo bit symbol default description 7:0 ch_stp[7:0] 11000000 lower8bitsof10bitcca(channelscan) stopchannelindex. word : ch_step address : 0ah bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) fstep[1] fstep[0] ch_stp[9] ch_stp[8] ch_sta[9] ch_ sta[8] ch[9] ch[8] wo wo wo wo wo wo rw rw bit symbol default description cca(channelscan)frequencystep: 00 50khz 01 100khz 10 200khz 7:6 fstep[1:0] 01 11 reserved 5:4 ch_stp[9:8] 11 highest2bitsof10bitcca(channelscan)stopch annelindex: stopfreqis(60+ch_stp*0.05)mhz. 3:2 ch_sta[9:8] 10 highest2bitsof10bitcca(channelscan)star tchannelindex: startfreqis(60+ch_sta*0.05)mhz. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page26 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 1:0 ch[9:8] 10 highest2bitsof10bitchannelindex: channelfreqis(60+ch*0.05)mhz. word : rdsd0 address : 0bh (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdsd0[7] rdsd0[6] rdsd0[5] rdsd0[4] rdsd0[3] rdsd0[ 2] rdsd0[1] rdsd0[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rdsd0[7:0] xxxxxxxx rdsdatabyte0. word : rdsd1 address : 0ch (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdsd1[7] rdsd1[6] rdsd1[5] rdsd1[4] rdsd1[3] rdsd1[ 2] rdsd1[1] rdsd1[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rdsd1[7:0] xxxxxxxx rdsdatabyte1. word : rdsd2 address : 0dh (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdsd2[7] rdsd2[6] rdsd2[5] rdsd2[4] rdsd2[3] rdsd2[ 2] rdsd2[1] rdsd2[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rdsd2[7:0] xxxxxxxx rdsdatabyte2. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page27 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : rdsd3 address : 0eh (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdsd3[7] rdsd3[6] rdsd3[5] rdsd3[4] rdsd3[3] rdsd3[ 2] rdsd3[1] rdsd3[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rdsd3[7:0] xxxxxxxx rdsdatabyte3. word : rdsd4 address : 0fh (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdsd4[7] rdsd4[6] rdsd4[5] rdsd4[4] rdsd4[3] rdsd4[ 2] rdsd4[1] rdsd4[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rdsd4[7:0] xxxxxxxx rdsdatabyte4. word : rdsd5 address : 10h (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdsd5[7] rdsd5[6] rdsd5[5] rdsd5[4] rdsd5[3] rdsd5[ 2] rdsd5[1] rdsd5[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rdsd5[7:0] xxxxxxxx rdsdatabyte5. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page28 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : rdsd6 address : 11h (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdsd6[7] rdsd6[6] rdsd6[5] rdsd6[4] rdsd6[3] rdsd6[ 2] rdsd6[1] rdsd6[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rdsd6[7:0] xxxxxxxx rdsdatabyte6. word : rdsd7 address : 12h (rw) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rdsd7[7] rdsd7[6] rdsd7[5] rdsd7[4] rdsd7[3] rdsd7[ 2] rdsd7[1] rdsd7[0] ro ro ro ro ro ro ro ro bit symbol default description 7:0 rdsd7[7:0] xxxxxxxx rdsdatabyte7. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page29 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : status2 address : 13h (ro) bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rds_rxtxupd e_det rdsc0c1 rdssync rdsd0err rdsd1err rdsd2err rd sd3err ro ro ro ro ro ro ro ro bit symbol default description rdsrx:rdsreceivedgroupupdated.eachtimeanew groupis received,thisbitwillbetoggled. ifrds_int_en=1,thenatthesametimethisbitis toggled,theinterrupt outputpin(int)willoutputa4.5mslowpulse. 0>1or1>0 anewset(8bytes)ofdataisreceived. 7 rds_rxtxupd r 0>0or1>1 newdataisinreceiving. eblock(mmbsblock)detected: 0 notdetected 6 e_det r 1 detected typeindicatoroftherdsthirdblockinonegroup: 0 c0 5 rdsc0c1 r 1 c1 rdsblocksynchronousindicator: 0 nonsynchronous 4 rdssync r 1 synchronous receivedrdsblock0statusindicator: 0 noerror 3 rds0err r 1 error receivedrdsblock1statusindicator: 0 noerror 2 rds1err r 1 error receivedrdsblock2statusindicator: 0 noerror 1 rds2err r 1 error receivedrdsblock3statusindicator: 0 noerror 0 rds3err r 1 error free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page30 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : vol_ctl address : 14h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) mute_en tc gain_dig[2] gain_dig[1] gain_dig[0] gain_ana[2] gain_ana[1] gain_ana[0] wo wo wo wo wo wo wo wo bit symbol default description rxaudiomuteenable: 0 nomute. 7 mute_en 0 1 mute preemphasisanddeemphasistimeconstant 0 50us 6 tc 1 1 75us gain_dig[2:0]setdigitalvolumegain: 101 5db 100 4db 011 3db 010 2db 001 1db 5:3 gain_dig[2:0] 000 000 0db lowerbitsofgain_ana[2:0]:setsvolumecontrolga inofanalog portion. 111 0db 110 6db 101 12db 100 18db 011 24db 010 30db 001 36db 2:0 gain_ana[2:0] 111 000 42db free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page31 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : xtal_div0 address : 15h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) xtal_div[7] xtal_div[6] xtal_div[5] xtal_div[4] xtal_div[3] xtal_div[2] xtal_div[1] xtal_div[0] wo wo wo wo wo wo wo wo bit symbol default description 7:0 xtal_div[7:0] 00000001 lower8bitsofxtal_div[10:0]. xtal_div[10:0]=round(freqofxtal/32.768khz). word : xtal_div1 address : 16h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) pll_dlt[4] pll_dlt[3] pll_dlt[2] pll_dlt[1] pll_dlt [0] xtal_div[10] xtal_div[9] xtal_div[8] wo wo wo wo wo wo wo wo bit symbol default description 7:3 pll_dlt[4:0] 00001 lower5bitsofpll_dlt[12:0]. 2:0 xtal_div[10:8] 000 higher3bitsofxtal_div[10:0]. xtal_div[10:0]=round(freqofxtal/32.768khz) word : xtal _div2 address : 17h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) pll_dlt[12] pll_dlt[11] pll_dlt[10] pll_dlt[9] pll_dlt[8] pll_dlt[7] pll_dl t[6] pll_dlt[5] wo wo wo wo wo wo wo wo bit symbol default description 7:0 pll_dlt[12:5] 01011100 higher8bitsofpll_dlt[12:0]. pll_dlt[12:0]=round(28.5mhz/(freq xtal /xtal_div[10:0]/512))442368. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page32 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. word : int_ctrl address : 18h bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) rds_int_en cca_int_en rds_only s1k_en rds_4k_en rsvd rsvd rsvd wo wo wo wo wo wo wo wo bit symbol default description rdsrxinterruptenable.whenrds_int_en=1,a4.5ms lowpulse willbeoutputfrompaddin(rxmode)whenanewgr oupdatais receivedandstoredintords0~rds7(rxmode). rds_int_en status 0 0 7 rds_int_en 0 1 1 rxccainterruptenable.whencca_int_en=1,a4.5ms lowpulse willbeoutputfrompaddin(rxmode)whenarxcca (rxmode)is finished. cca_int_en status 0 disable 6 cca_int_en 0 1 enable rdsmode rds_only rdsmodeselection 0 receivedbitstreamhavebothrdsandmmbs blocks(eblock) 5 rds_only 1 1 receivedbitstreamhasrdsblockonly,no mmbsblock(eblock) internal1ktoneselection.itwillbeusedasdac outputwhenrxreq. 0 disable 4 s1k_en 0 1 enable 3 rds_4k_en 0 enablerds4kmode. 2:0 rsvd 000 reserved. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page33 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 7 ordering information part number description package QN8035ncna theQN8035ncnaissinglechiplowpowe rfm receiver. 2.5x2.5mmbody [qfn16] QN8035sana theQN8035sanapiniscompatiblewith the qn8005/8005b. 3x3mmbody [msop10] free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page34 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 8 package description 16-lead plastic quad flat, no lead package (ml) C 2 .5x2.5 mm body [qfn] figure 13 QN8035 mechanical drawing units millimeters dimension limits min nom max numberofpins 16 pitch 0.50bsc overallheight slp 0.70 0.75 0.80 standoff 0.00 0.05 contactthickness 0.203ref overallwidth 2.50bsc exposedpadwidth 1.35 1.40 1.45 overalllength 2.50bsc exposedpadlength 1.35 1.40 1.45 cornercontactheight&width 0.25 0.30 0.35 sidecontactwidth 0.18 0.23 0.28 sidecontactlength 0.25 0.30 0.35 contacttoexposedpad 0.25 notes: free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page35 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 1. pin1visualindexfeaturemayvary,butmustbelo catedwithinthehatchedarea. 2. packageissawsingulated. 3. dimensioningandtoleranceperasmey14.5m. bsc:basicdimension.thetheoreticallyexactvalue isshownwithouttolerance. ref:referencedimension,usuallywithouttolerance ,forinformationpurposeonly. 10-lead plastic quad flat, no lead package (ml) C 3 x3 mm body [qfn] figure 14 msop10 package outline dimensions millimeters symbol description minimum nominal maximum a overallpackageheight 0.820 0.95 1.100 a1 boardstandoff 0.020 0.150 a2 packagethickness 0.750 0.85 0.950 b leadwidth 0.180 0.23 0.280 c leadthickness 0.090 0.230 d packagesoutside,xaxis 2.900 3.00 3.100 e leadpitch 0.50(bsc) e packagesoutside,yaxis 2.900 3.00 3.100 e1 leadtolead,yaxis 4.750 4.90 5.050 l footlength 0.400 0.60 0.800 foottoboardangle 0 6 notes: 1. pin1visualindexfeaturemayvary,butmustbelo catedwithintheareaindicatedinthedrawing. 2. dimensioningandtoleranceperasmey14.5m. bsc:basicdimension.thetheoreticallyexactvalue isshownwithouttolerance. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page36 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. carrier tape dimensions figure 15 2.5x2.5 qfn16 carrier tape notes: 1. 10sprocketholepitchcumulativetolerance 0.2. 2. camberincompliancewitheia481. 3. pocketpositionrelativetosprocketholemeasured astruepositionofpocket,notpockethole. 4. a0=2.81 b0=2.85 k0=1.00 free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page37 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 3x3 msop10 carrier tape figure 16 msop10 carrier tape drawing notes: 1. 10sprocketholepitchcumulativetolerance+ u 0.2mmmaximum. 2. cambernottoexceed1mmin100mm:< 1mm/100mm. 3. pocketpositionrelativetosprocketholemeasur ed astruepositionofpocket,notpockethole. free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page38 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 9 solder reflow profile 9.1 package peak reflow temperature QN8035areassembledinaleadfreeqfn24andmsop1 0packages.sincethegeometricalsizeofQN8035is 4mm 4 mm 0.85mm,thevolumeandthicknessisinthecatego ryofvolume<350mm 3 andthickness<1.6mmintable42of ipc/jedecjstd020c.thepeakreflowtemperaturei s: c 260 t o p = thetemperaturetoleranceis+0 o cand5 o c.temperatureismeasuredatthetopofthepackag e. 9.2 classification reflow profiles profile feature specification* average ramp-up rate (tsmax to tp) 3c/second max. temperature min (tsmin) 150c temperature max (tsmax) 200c pre-heat: time (ts) 60-180 seconds temperature (t l ) 217c time maintained above: time (t l ) 60-150 seconds peak/classification temperature (tp) 260c time within 5c of actual peak temperature (tp) 20-40 seconds ramp-down rate 6c/second max. time 25c to peak temperature 8 minutes max. *note:alltemperaturesaremeasuredatthetopof thepackage. figure 1: reflow temperature profile free datasheet http:///
QN8035 rev0.08(02/10) copyright?2010byquinticcorpora tion page39 confidential a confidentialinformationcontainedhereiniscover edundernondisclosureagreement(nda). advancetechnicalinformation.thisisaproductun derdevelopment.characteristicsandspecifications aresubjecttochangewithoutnotice. 9.3 maximum reflow times allpackagereliabilitytestswereperformedandpa ssedwithapreconditionprocedurethatrepeatar eflowprofile,which conformstotherequirementsinsection9.2, three (3) times. contact information quintic corporation (usa) 3211scottblvd.,suite203 santaclara,ca95054 tel:+1.408.970.8808 fax:+1.408.970.8829 email: hu support@quinticcorp.com u web: hu www.quinticcorp.com u quintic microelectronics (china) building8b301atsinghuasciencepark 1steastzhongguancunrd,haidian beijing,china100084 tel:+86(10)82151997 fax:+86(10)82151570 web: h www.quinticcorp.com quinticmicroelectronicsandquinticaretrademarks ofquinticcorporation.allrightsreserved. free datasheet http:///

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